// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T1 Processor File: Ni_MmuState.cc
// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
// 
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
// 
// The above named program is distributed in the hope that it will be 
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
// General Public License for more details.
// 
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
// 
// ========== Copyright Header End ============================================
/************************************************************************
**  
**  Copyright (C) 2002, Sun Microsystems, Inc.
**
**  Sun considers its source code as an unpublished, proprietary
**  trade secret and it is available only under strict license provisions.
**  This copyright notice is placed here only to protect Sun in the event 
**  the source is deemed a published work. Disassembly, decompilation,
**  or other means of reducing the object code to human readable form
**  is prohibited by the license agreement under which this code is
**  provided to the user or company in possession of this copy."
**
*************************************************************************/
#include "Ni/Ni_MmuState.h"
#include "Sf/Sf_MmuState.h"
#include "StdMacros.h"
#include <sstream>

using namespace std;
using namespace Riesling;
Ni_MmuState::Ni_MmuState()
{
}

Ni_MmuState::Ni_MmuState( const Ni_MmuState & orig ) :
	dTsbPs0Pointer_( orig.dTsbPs0Pointer_ ),
	dTsbPs1Pointer_( orig.dTsbPs1Pointer_ ),
	iTsbPs0Pointer_( orig.iTsbPs0Pointer_ ),
	iTsbPs1Pointer_( orig.iTsbPs1Pointer_ ),
	dTsbDirectPointer_( orig.dTsbDirectPointer_ ),
	dCtxtNonzeroConfig_( orig.dCtxtNonzeroConfig_ ),
	dCtxtNonzeroTsbBasePs0_( orig.dCtxtNonzeroTsbBasePs0_ ),
	dCtxtNonzeroTsbBasePs1_( orig.dCtxtNonzeroTsbBasePs1_ ),
	dCtxtZeroConfig_( orig.dCtxtZeroConfig_ ),
	dCtxtZeroTsbBasePs0_( orig.dCtxtZeroTsbBasePs0_ ),
	dCtxtZeroTsbBasePs1_( orig.dCtxtZeroTsbBasePs1_ ),
	iCtxtNonzeroConfig_( orig.iCtxtNonzeroConfig_ ),
	iCtxtNonzeroTsbBasePs0_( orig.iCtxtNonzeroTsbBasePs0_ ),
	iCtxtNonzeroTsbBasePs1_( orig.iCtxtNonzeroTsbBasePs1_ ),
	iCtxtZeroConfig_( orig.iCtxtZeroConfig_ ),
	iCtxtZeroTsbBasePs0_( orig.iCtxtZeroTsbBasePs0_ ),
	iCtxtZeroTsbBasePs1_( orig.iCtxtZeroTsbBasePs1_ ),
	idPartitionId_( orig.idPartitionId_ ),
	iTsbTagTarget_( orig.iTsbTagTarget_ ),
	dTsbTagTarget_( orig.dTsbTagTarget_ ),
	iTlbTagAccess_( orig.iTlbTagAccess_ ),
	dTlbTagAccess_( orig.dTlbTagAccess_ ),
	iSfsr_( orig.iSfsr_ ),
	dSfsr_( orig.dSfsr_ ),
	syncFaultAddress_( orig.syncFaultAddress_ ),
	primaryDContext_( orig.primaryDContext_ ),
	secondaryContext_( orig.secondaryContext_ ),
	virtualWatchpoint_( orig.virtualWatchpoint_ ),
	iDataIn_( orig.iDataIn_ ),
	dDataIn_( orig.dDataIn_ ),
	iDataAccess_( orig.iDataAccess_ ),
	dDataAccess_( orig.dDataAccess_ )

{}

Ni_MmuState::~Ni_MmuState()
{}

const Ni_MmuState &
Ni_MmuState::operator=( const Ni_MmuState & rhs )
{
 
    return *this;
}

bool
Ni_MmuState::operator==( const Ni_MmuState & rhs ) const
{ 
    return 
	dTsbPs0Pointer_ == rhs.dTsbPs0Pointer_ &&
	dTsbPs1Pointer_ == rhs.dTsbPs1Pointer_ &&
	iTsbPs0Pointer_ == rhs.iTsbPs0Pointer_ &&
	iTsbPs1Pointer_ == rhs.iTsbPs1Pointer_ &&
	dTsbDirectPointer_ == rhs.dTsbDirectPointer_ &&
	dCtxtNonzeroConfig_ == rhs.dCtxtNonzeroConfig_ &&
	dCtxtNonzeroTsbBasePs0_ == rhs.dCtxtNonzeroTsbBasePs0_ &&
	dCtxtNonzeroTsbBasePs1_ == rhs.dCtxtNonzeroTsbBasePs1_ &&
	dCtxtZeroConfig_ == rhs.dCtxtZeroConfig_ &&
	dCtxtZeroTsbBasePs0_ == rhs.dCtxtZeroTsbBasePs0_ &&
	dCtxtZeroTsbBasePs1_ == rhs.dCtxtZeroTsbBasePs1_ &&
	iCtxtNonzeroConfig_ == rhs.iCtxtNonzeroConfig_ &&
	iCtxtNonzeroTsbBasePs0_ == rhs.iCtxtNonzeroTsbBasePs0_ &&
	iCtxtNonzeroTsbBasePs1_ == rhs.iCtxtNonzeroTsbBasePs1_ &&
	iCtxtZeroConfig_ == rhs.iCtxtZeroConfig_ &&
	iCtxtZeroTsbBasePs0_ == rhs.iCtxtZeroTsbBasePs0_ &&
	iCtxtZeroTsbBasePs1_ == rhs.iCtxtZeroTsbBasePs1_ &&
	idPartitionId_ == rhs.idPartitionId_ &&
	iTsbTagTarget_ == rhs.iTsbTagTarget_ &&
	dTsbTagTarget_ == rhs.dTsbTagTarget_ &&
	iTlbTagAccess_ == rhs.iTlbTagAccess_ &&
	dTlbTagAccess_ == rhs.dTlbTagAccess_ &&
	iSfsr_ == rhs.iSfsr_ &&
	dSfsr_ == rhs.dSfsr_ &&
	syncFaultAddress_ == rhs.syncFaultAddress_ &&
	primaryDContext_ == rhs.primaryDContext_ &&
	secondaryContext_ == rhs.secondaryContext_ &&
	virtualWatchpoint_ == rhs.virtualWatchpoint_ &&
	iDataIn_ == rhs.iDataIn_ &&
	dDataIn_ == rhs.dDataIn_ &&
	iDataAccess_ == rhs.iDataAccess_ &&
	dDataAccess_ == rhs.dDataAccess_ ;

}

string
Ni_MmuState::toString() const
{
    ostringstream os;



	os << "dSfsr_: 0x" <<  hex << dSfsr_.getNative() << ":" << dSfsr_.toString() << endl;

	os << "iSfsr_: 0x" <<  hex << iSfsr_.getNative() << ":" << iSfsr_.toString() << endl;

	os << "syncFaultAddress_ : 0x" <<  hex << syncFaultAddress_ << endl;

	os << "dTlbTagAccess_: 0x" <<  hex << dTlbTagAccess_.getNative();
	os << ":" << dTlbTagAccess_.toString() << endl;

	os << "iTlbTagAccess_: 0x" <<  hex << iTlbTagAccess_.getNative();
	os << ":" << iTlbTagAccess_.toString() << endl;

	os << endl;

	os << "dTsbPs0Pointer_ : 0x" <<  hex << dTsbPs0Pointer_ << endl;
	os << "dTsbPs1Pointer_ : 0x" <<  hex << dTsbPs1Pointer_ << endl;
	os << "dTsbDirectPointer_ : 0x" <<  hex << dTsbDirectPointer_ << endl;

	os << "dCtxtZeroConfig_: 0x" <<  hex << dCtxtZeroConfig_.getNative();
	os << ":" << dCtxtZeroConfig_.toString() << endl;
	os << "dCtxtNonzeroConfig_: 0x" <<  hex << dCtxtNonzeroConfig_.getNative();
	os << ":" << dCtxtNonzeroConfig_.toString() << endl;

	os << "dCtxtZeroTsbBasePs0_: 0x" <<  hex << dCtxtZeroTsbBasePs0_.getNative();
	os << ":" << dCtxtZeroTsbBasePs0_.toString() << endl;
	os << "dCtxtZeroTsbBasePs1_: 0x" <<  hex << dCtxtZeroTsbBasePs1_.getNative();
	os << ":" << dCtxtZeroTsbBasePs1_.toString() << endl;

	os << "dCtxtNonzeroTsbBasePs0_: 0x" <<  hex << dCtxtNonzeroTsbBasePs0_.getNative();
	os << ":" << dCtxtNonzeroTsbBasePs0_.toString() << endl;
	os << "dCtxtNonzeroTsbBasePs1_: 0x" <<  hex << dCtxtNonzeroTsbBasePs1_.getNative();
	os << ":" << dCtxtNonzeroTsbBasePs1_.toString() << endl;

	os << "dTsbTagTarget_: 0x" <<  hex << dTsbTagTarget_.getNative();
	os << ":" << dTsbTagTarget_.toString() << endl;

	os << endl;

	os << "iTsbPs0Pointer_ : 0x" <<  hex << iTsbPs0Pointer_ << endl;
	os << "iTsbPs1Pointer_ : 0x" <<  hex << iTsbPs1Pointer_ << endl;

	os << "iCtxtZeroConfig_: 0x" <<  hex << iCtxtZeroConfig_.getNative();
	os << ":" << iCtxtZeroConfig_.toString() << endl;
	os << "iCtxtNonzeroConfig_: 0x" <<  hex << iCtxtNonzeroConfig_.getNative();
	os << ":" << iCtxtNonzeroConfig_.toString() << endl;

	os << "iCtxtZeroTsbBasePs0_: 0x" <<  hex << iCtxtZeroTsbBasePs0_.getNative();
	os << ":" << iCtxtZeroTsbBasePs0_.toString() << endl;
	os << "iCtxtZeroTsbBasePs1_: 0x" <<  hex << iCtxtZeroTsbBasePs1_.getNative();
	os << ":" << iCtxtZeroTsbBasePs1_.toString() << endl;

	os << "iCtxtNonzeroTsbBasePs0_: 0x" <<  hex << iCtxtNonzeroTsbBasePs0_.getNative();
	os << ":" << iCtxtNonzeroTsbBasePs0_.toString() << endl;
	os << "iCtxtNonzeroTsbBasePs1_: 0x" <<  hex << iCtxtNonzeroTsbBasePs1_.getNative();
	os << ":" << iCtxtNonzeroTsbBasePs1_.toString() << endl;

	os << "idPartitionId_: 0x" <<  hex << idPartitionId_.getNative();
	os << ":" << idPartitionId_.toString() << endl;

	os << "iTsbTagTarget_: 0x" <<  hex << iTsbTagTarget_.getNative();
	os << ":" << iTsbTagTarget_.toString() << endl;
	
	os << endl;

	os << "primaryDContext_ : 0x" <<  hex << primaryDContext_.getNative() << endl;
	os << "secondaryContext_ : 0x" <<  hex << secondaryContext_.getNative() << endl;

	os << virtualWatchpoint_.toString() << endl;

	os << "iDataIn_ : 0x" <<  hex << iDataIn_ << endl;
	os << "dDataIn_ : 0x" <<  hex << dDataIn_ << endl;
	os << "iDataAccess_ : 0x" <<  hex << iDataAccess_ << endl;
	os << "dDataAccess_ : 0x" <<  hex << dDataAccess_ << endl;

    return os.str();

}


///////////////////////////////////////////////////////////////////////////////////////

Ni_MmuConfigReg *
Ni_MmuState::getdCtxtNonzeroConfigPtr()
{
	return &dCtxtNonzeroConfig_;
}

VaddrT
Ni_MmuState::getdTsbPs0Pointer() const
{
	return dTsbPs0Pointer_;
}


void
Ni_MmuState::setdTsbPs0Pointer(VaddrT va)
{
	dTsbPs0Pointer_ = va;
}

Ni_TsbBaseReg *
Ni_MmuState::getiCtxtZeroTsbBasePs0Ptr()
{
	return &iCtxtZeroTsbBasePs0_;
}

Ni_TsbBaseReg *
Ni_MmuState::getdCtxtNonzeroTsbBasePs0Ptr()
{
	return &dCtxtNonzeroTsbBasePs0_;
}

VaddrT
Ni_MmuState::getdTsbPs1Pointer() const
{
	return dTsbPs1Pointer_;
}

void
Ni_MmuState::setdTsbPs1Pointer(VaddrT va)
{
	dTsbPs1Pointer_ = va;
}

Ni_TsbBaseReg *
Ni_MmuState::getiCtxtZeroTsbBasePs1Ptr()
{
	return &iCtxtZeroTsbBasePs1_;
}

Ni_TsbBaseReg *
Ni_MmuState::getdCtxtNonzeroTsbBasePs1Ptr()
{
	return &dCtxtNonzeroTsbBasePs1_;
}


Ni_IDPartitionIdReg *
Ni_MmuState::getidPartitionIdPtr()
{
	return &idPartitionId_;
}

Ni_MmuConfigReg *
Ni_MmuState::getdCtxtZeroConfigPtr()
{
	return &dCtxtZeroConfig_;
}

Ni_VaWatchpointReg *
Ni_MmuState::getVirtualWatchpointPtr()
{
	return &virtualWatchpoint_;
}


Ni_TsbBaseReg *
Ni_MmuState::getdCtxtZeroTsbBasePs0Ptr()
{
	return &dCtxtZeroTsbBasePs0_;
}

Ni_MmuConfigReg *
Ni_MmuState::getiCtxtNonzeroConfigPtr()
{
	return &iCtxtNonzeroConfig_;
}

Ni_TsbBaseReg *
Ni_MmuState::getdCtxtZeroTsbBasePs1Ptr()
{
	return &dCtxtZeroTsbBasePs1_;
}

Ni_TsbBaseReg *
Ni_MmuState::getiCtxtNonzeroTsbBasePs0Ptr()
{
	return &iCtxtNonzeroTsbBasePs0_;
}

VaddrT
Ni_MmuState::getiTsbPs0Pointer() const
{
	return iTsbPs0Pointer_;
}

void
Ni_MmuState::setiTsbPs0Pointer( VaddrT va)
{
	iTsbPs0Pointer_ = va;
}

Ni_TsbBaseReg *
Ni_MmuState::getiCtxtNonzeroTsbBasePs1Ptr()
{
	return &iCtxtNonzeroTsbBasePs1_;
}

VaddrT
Ni_MmuState::getiTsbPs1Pointer() const
{
	return iTsbPs1Pointer_;
}

void
Ni_MmuState::setiTsbPs1Pointer( VaddrT va )
{
	iTsbPs1Pointer_ = va;
}

VaddrT
Ni_MmuState::getdTsbDirectPointer() const
{
    if(isTsbDirectPointerPs0_ ) {
	return dTsbPs0Pointer_;
    } else {
	return dTsbPs1Pointer_;
    }
}

void
Ni_MmuState::setdTsbDirectPointer( VaddrT va)
{
    if(isTsbDirectPointerPs0_ ) {
	dTsbPs0Pointer_ = va; 
    } else {
	dTsbPs1Pointer_ = va; 
    }

}

Ni_MmuConfigReg *
Ni_MmuState::getiCtxtZeroConfigPtr()
{
	return &iCtxtZeroConfig_;
}

Sf_TagTargetReg *
Ni_MmuState::getiTsbTagTargetPtr()
{
	return &iTsbTagTarget_;
}

Sf_TagTargetReg *
Ni_MmuState::getdTsbTagTargetPtr()
{
    return &dTsbTagTarget_;
}


Sf_TagAccessReg *
Ni_MmuState::getiTlbTagAccessPtr()
{
    return &iTlbTagAccess_;
}

Sf_TagAccessReg *
Ni_MmuState::getdTlbTagAccessPtr()
{
    return &dTlbTagAccess_;
}

///////////////////////////////////////////////////////////////////////////////////////



ContextT
Ni_MmuState::getPrimaryDContext() const
{
    return primaryDContext_.getCONTEXT();
}

ContextT
Ni_MmuState::getSecondaryContext() const
{
    return secondaryContext_.getCONTEXT();
}


void
Ni_MmuState::setPrimaryDContext( ContextT ctxt )
{
    primaryDContext_.setCONTEXT( ctxt );
}

void 
Ni_MmuState::setSecondaryContext( ContextT ctxt )
{
    secondaryContext_.setCONTEXT(ctxt);
}

Sf_SfsReg *
Ni_MmuState::getiSfsrPtr()
{
    return &iSfsr_;
}

Sf_SfsReg *
Ni_MmuState::getdSfsrPtr()
{
    return &dSfsr_;
}

VaddrT 
Ni_MmuState::getSyncFaultAddress() const
{
    return syncFaultAddress_;
}


void
Ni_MmuState::setSyncFaultAddress(VaddrT v)
{
    syncFaultAddress_ = v;
}



Uint64T
Ni_MmuState::getiDataIn() const
{
    return iDataIn_;
}

Uint64T
Ni_MmuState::getdDataIn() const
{
    return dDataIn_;
}


Uint64T
Ni_MmuState::getiDataAccess() const
{
    return iDataAccess_;
}


Uint64T
Ni_MmuState::getdDataAccess() const
{
    return dDataAccess_;
}

void
Ni_MmuState::setiDataIn(Uint64T v)
{
	iDataIn_ = v;
}

void
Ni_MmuState::setdDataIn(Uint64T v)
{
	dDataIn_ = v;
}


void
Ni_MmuState::setiDataAccess(Uint64T v)
{
	iDataAccess_ = v;
}


void
Ni_MmuState::setdDataAccess(Uint64T v)
{
	dDataAccess_ = v;
}

void
Ni_MmuState::isTsbDirectPointerPs0(bool s)
{
    isTsbDirectPointerPs0_ = s;
}

bool
Ni_MmuState::isTsbDirectPointerPs0()
{
    return isTsbDirectPointerPs0_;
}

void 
Ni_MmuState::snapshot( SS_SnapShot &ss, const char *prefix )
{
    sprintf(ss.tag,"%s.isTsbDirectPointerPs0",prefix);	ss.val(&isTsbDirectPointerPs0_);

    sprintf(ss.tag,"%s.d0ptr",prefix);			ss.val(&dTsbPs0Pointer_);
    sprintf(ss.tag,"%s.d1ptr",prefix);			ss.val(&dTsbPs1Pointer_);
    sprintf(ss.tag,"%s.i0ptr",prefix);			ss.val(&iTsbPs0Pointer_);
    sprintf(ss.tag,"%s.i1ptr",prefix);			ss.val(&iTsbPs1Pointer_);
    sprintf(ss.tag,"%s.dptr",prefix);			ss.val(&dTsbDirectPointer_);

    char extended_prefix[SS_SnapShot::LINE_SIZE];
    sprintf(extended_prefix,"%s.dctxtNzc",prefix);	dCtxtNonzeroConfig_.snapshot(ss,extended_prefix);
    sprintf(extended_prefix,"%s.dctxtNz0",prefix);	dCtxtNonzeroTsbBasePs0_.snapshot(ss,extended_prefix);
    sprintf(extended_prefix,"%s.dctxtNz1",prefix);	dCtxtNonzeroTsbBasePs1_.snapshot(ss,extended_prefix);

    sprintf(extended_prefix,"%s.dctxtZc",prefix);	dCtxtZeroConfig_.snapshot(ss,extended_prefix);
    sprintf(extended_prefix,"%s.dctxtZ0",prefix);	dCtxtZeroTsbBasePs0_.snapshot(ss,extended_prefix);
    sprintf(extended_prefix,"%s.dctxtZ1",prefix);	dCtxtZeroTsbBasePs1_.snapshot(ss,extended_prefix);

    sprintf(extended_prefix,"%s.ictxtNzc",prefix);	iCtxtNonzeroConfig_.snapshot(ss,extended_prefix);
    sprintf(extended_prefix,"%s.ictxtNz0",prefix);	iCtxtNonzeroTsbBasePs0_.snapshot(ss,extended_prefix);
    sprintf(extended_prefix,"%s.ictxtNz1",prefix);	iCtxtNonzeroTsbBasePs1_.snapshot(ss,extended_prefix);

    sprintf(extended_prefix,"%s.ictxtZc",prefix);	iCtxtZeroConfig_.snapshot(ss,extended_prefix);
    sprintf(extended_prefix,"%s.ictxtZ0",prefix);	iCtxtZeroTsbBasePs0_.snapshot(ss,extended_prefix);
    sprintf(extended_prefix,"%s.ictxtZ1",prefix);	iCtxtZeroTsbBasePs1_.snapshot(ss,extended_prefix);

    sprintf(extended_prefix,"%s.idPartitionId",prefix);	idPartitionId_.snapshot(ss,extended_prefix);
    sprintf(extended_prefix,"%s.iTagTarget",prefix);	iTsbTagTarget_.snapshot(ss,extended_prefix);
    sprintf(extended_prefix,"%s.dTagTarget",prefix);	dTsbTagTarget_.snapshot(ss,extended_prefix);
	
    sprintf(extended_prefix,"%s.iTagAccess",prefix);	iTlbTagAccess_.snapshot(ss,extended_prefix);
    sprintf(extended_prefix,"%s.dTagAccess",prefix);	dTlbTagAccess_.snapshot(ss,extended_prefix);

    sprintf(extended_prefix,"%s.isfsr",prefix);		iSfsr_.snapshot(ss,extended_prefix);
    sprintf(extended_prefix,"%s.dsfsr",prefix);		dSfsr_.snapshot(ss,extended_prefix);

    sprintf(ss.tag,"%s.syncFaultAddr",prefix);		ss.val(&syncFaultAddress_);

    sprintf(extended_prefix,"%s.primDcontext",prefix);	primaryDContext_.snapshot(ss,extended_prefix);
    sprintf(extended_prefix,"%s.secDcontext",prefix);	secondaryContext_.snapshot(ss,extended_prefix);

    sprintf(extended_prefix,"%s.virtWatchPt",prefix);	virtualWatchpoint_.snapshot(ss,extended_prefix);

    sprintf(ss.tag,"%s.idataIn",prefix);		ss.val(&iDataIn_);
    sprintf(ss.tag,"%s.idataAccess",prefix);		ss.val(&iDataAccess_);
    sprintf(ss.tag,"%s.ddataIn",prefix);		ss.val(&dDataIn_);
    sprintf(ss.tag,"%s.ddataAccess",prefix);		ss.val(&dDataAccess_);
}
